STG-based resynthesis for balsa circuits

Balsa provides a rapid development flow, where asynchronous circuits are created from high-level specifications, but the syntax-driven translation used by the Balsa compiler often results in performance overhead. To reduce this performance penalty, various control resynthesis and peephole optimization techniques are used; in this paper, STG-based resynthesis is considered. For this, we have translated the control parts of almost all components used by the Balsa compiler into STGs; in particular we separated the control path and the data path in the data components. A Balsa specification corresponds to the parallel composition of such STGs, but this composition must be reduced. We have developed new reduction operations and, using real-life examples, studied various strategies how to apply them. This research was supported by DFG-project 'Optacon' VO 615/10-1 and WO 814/3-1. This report is the full version of the extended abstract.

Metadaten
Author:	Stanislavs Golubcovs, Walter Vogler GND, Norman Kluge
URN:	urn:nbn:de:bvb:384-opus4-25041
Frontdoor URL	https://opus.bibliothek.uni-augsburg.de/opus4/2504
Series (Serial Number):	Reports / Technische Berichte der Fakultät für Angewandte Informatik der Universität Augsburg (2013-12)
Type:	Report
Language:	English
Publishing Institution:	Universität Augsburg
Release Date:	2013/11/08
Institutes:	Fakultät für Angewandte Informatik
	Fakultät für Angewandte Informatik / Institut für Informatik
	Fakultät für Angewandte Informatik / Institut für Informatik / Lehrstuhl für Softwaretechnik
	Fakultät für Angewandte Informatik / Institut für Informatik / Lehrstuhl für Softwaretechnik / Professur für Theorie verteilter Systeme
Dewey Decimal Classification:	0 Informatik, Informationswissenschaft, allgemeine Werke / 00 Informatik, Wissen, Systeme / 004 Datenverarbeitung; Informatik
Licence (German):	Deutsches Urheberrecht

Open Access