ISPTAP - Instruction Scratchpad Timing Analysis Program: Features and Usage

  • The Instruction Scratchpad Timing Analysis Program (ISPTAP) is a static timing analysis tool developed for the D-ISP (dynamic instruction scratchpad). It features the timing analysis of the CarCore and the ARM Cortex M0 processors and supports common instruction memories of embedded systems, like caches and scratchpads. In this report we describe the timing analysis tool including the timing models of the supported architectures. To validate the timing models we quantify the overestimation of the calculated WCETs compared to the measured execution times obtained from cycle-accurate processor simulators. Furthermore, we describe the usage and the configuration of the ISPTAP tool.

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Author:Stefan Metzlaff
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Series (Serial Number):Reports / Technische Berichte der Fakultät für Angewandte Informatik der Universität Augsburg (2013-09)
Publishing Institution:Universität Augsburg
Release Date:2013/08/01
Tag:timing analysis tool; WCET; hard real-time; instruction memories
Institutes:Fakultät für Angewandte Informatik
Fakultät für Angewandte Informatik / Institut für Informatik
Dewey Decimal Classification:0 Informatik, Informationswissenschaft, allgemeine Werke / 00 Informatik, Wissen, Systeme / 004 Datenverarbeitung; Informatik
Licence (German):Deutsches Urheberrecht