parMERASA Pattern Catalogue: Timing Predictable Parallel Design Patterns

  • The aim of this catalogue is to describe parallel design patterns and synchronization idioms suitable for the development of parallel software for embedded systems supporting WCET analysis. It is written in context of the parMERASA FP7 project. It represents the state of knowledge after 24 month of the project, where parallelization concepts have been developed for all industrial applications. This catalogue is the basis for the Pattern-supported Parallelisation Approach, which is a model-based approach for the transition from sequential code to parallel code. In the scope of parMERASA, a timing analyzable implementation for some parallel design patterns, which is called Timing-analyzable Algorithmic Skeletons (TAS), is being developed which will ease the implementation of the patterns. Also further timing predictable parallel design patterns and synchronization idioms might be developed or discovered in the remainder of the project, as well as the examples in currently availableThe aim of this catalogue is to describe parallel design patterns and synchronization idioms suitable for the development of parallel software for embedded systems supporting WCET analysis. It is written in context of the parMERASA FP7 project. It represents the state of knowledge after 24 month of the project, where parallelization concepts have been developed for all industrial applications. This catalogue is the basis for the Pattern-supported Parallelisation Approach, which is a model-based approach for the transition from sequential code to parallel code. In the scope of parMERASA, a timing analyzable implementation for some parallel design patterns, which is called Timing-analyzable Algorithmic Skeletons (TAS), is being developed which will ease the implementation of the patterns. Also further timing predictable parallel design patterns and synchronization idioms might be developed or discovered in the remainder of the project, as well as the examples in currently available design patterns will be updated with lessons learned from the parallelization of industrial applications in the parMERASA project. In that case a second edition of this pattern catalogue will be published.show moreshow less

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Metadaten
Author:Mike Gerdes, Ralf Jahr, Theo UngererORCiDGND
URN:urn:nbn:de:bvb:384-opus4-24750
Frontdoor URLhttps://opus.bibliothek.uni-augsburg.de/opus4/2475
Series (Serial Number):Reports / Technische Berichte der Fakultät für Angewandte Informatik der Universität Augsburg (2013-11)
Type:Report
Language:English
Publishing Institution:Universität Augsburg
Release Date:2013/09/27
Tag:embedded systems; hard real-time; parallel design pattern; parallelization; synchronisation
GND-Keyword:Echtzeitsystem; Entwurfsmuster; Mehrkernprozessor; Parallelisierung
Institutes:Fakultät für Angewandte Informatik / Informatik
Dewey Decimal Classification:0 Informatik, Informationswissenschaft, allgemeine Werke / 00 Informatik, Wissen, Systeme / 004 Datenverarbeitung; Informatik
Licence (German):License LogoVeröffentlichungsvertrag für Publikationen ohne Print on Demand