Efficient implementation of regular parallel adders for binary signed digit number representations
| Author: | Eberhard Zehendner |
|---|---|
| Frontdoor URL | https://opus.bibliothek.uni-augsburg.de/opus4/17498 |
| ISSN: | 0165-6074OPAC |
| Parent Title (English): | Microprocessing and Microprogramming |
| Publisher: | Elsevier Science |
| Place of publication: | Amsterdam |
| Type: | Article |
| Language: | English |
| Year of first Publication: | 1992 |
| Release Date: | 2017/07/21 |
| Volume: | 35 |
| Issue: | 1-5 |
| First Page: | 319 |
| Last Page: | 326 |
| DOI: | https://doi.org/10.1016/0165-6074(92)90334-4 |
| Institutes: | Mathematisch-Naturwissenschaftlich-Technische Fakultät |
| Mathematisch-Naturwissenschaftlich-Technische Fakultät / Institut für Mathematik |
